A CR2032 coin cell stores approximately 660 mWh of energy at a nominal 3V discharge. That number is fixed by electrochemistry — you cannot engineer around it in firmware. What you can control is the rate at which the inference system drains that budget, and understanding the physical constraints at each abstraction layer is the prerequisite to making rational design choices.
The CR2032 energy budget: what the datasheet doesn't explain
The 220–235 mAh capacity specification on a CR2032 is measured at low drain rates (typically 0.1 mA or lower). At drain rates above ~1 mA, internal resistance and manganese-dioxide cathode kinetics cause effective capacity to drop — typically to 150–180 mAh at 1 mA continuous. At 5 mA continuous drain, capacity can fall to 80–100 mAh.
This means that a system drawing 5 mA continuous (15 mW at 3V) doesn't last 660 mWh / 15 mW = 44 hours — it lasts closer to 18–22 hours. Inference systems that ignore this nonlinearity will produce optimistic projections that don't survive contact with hardware. For neuromorphic inference in the 40–200 µW range, the drain is low enough that the full 660 mWh is realistically available, and the capacity curve is essentially flat.
The 36-month constraint math
Three years of continuous deployment is a common requirement for industrial and environmental sensor nodes — replacing batteries in deployed infrastructure is expensive when nodes are physically inaccessible or geographically dispersed. 36 months = ~26,280 hours. From 660 mWh total:
P_budget = 660 mWh / 26,280 h = 25.1 µW (continuous average)25 µW average. That's the fundamental budget. Everything that consumes power in the system — sensor, radio, MCU sleep current, inference subsystem — must fit within this envelope. The inference subsystem typically gets 5–15 µW of that budget in a power-optimized design. The rest goes to sensor sampling (typically 2–8 µW for MEMS microphones or accelerometers in low-power mode), a radio that bursts at very low duty cycle, and the always-on supervisor circuit.
The power floor: static leakage vs dynamic inference
Any active circuit has two power components: static (leakage, retention) and dynamic (switching). For digital CMOS at sub-threshold supply voltages, leakage is a significant fraction of total power. Neuromorphic chips designed for always-on use cases are typically implemented in advanced process nodes (22nm FFL for Intel Loihi 2, 28nm for BrainChip Akida) partly to reduce leakage floor.
For Loihi 2 in a typical deployment configuration with most cores idle:
- Chip leakage (all cores in sleep): ~200–300 µW (entire chip including I/O)
- Active inference with 10% core utilization: ~400–800 µW
- Full 128-core utilization: ~2–4 mW
These numbers make Loihi 2 appropriate for systems with larger batteries or energy harvesting, not for single CR2032 deployments. Loihi 2 is a research and prototyping platform — Neurmorph uses it for algorithm development and benchmark reference, not as a target for coin-cell deployments.
For coin-cell inference targets, SynSense Xylo and BrainChip Akida AKD1000 are more relevant. Xylo's neuromorphic audio inference core draws approximately 15–30 µW for small inference networks (64–128 neurons), making it coin-cell compatible for tasks that fit within that neuron budget. AKD1000 in its lowest-power inference configuration draws roughly 300–500 µW, which puts it at the edge of coin-cell feasibility for very low duty-cycle applications (< 5% active inference time).
Thermodynamic floor: the Landauer limit isn't your problem
The Landauer limit — the theoretical minimum energy to erase one bit of information, kT ln 2 ≈ 3×10-21 J at room temperature — is sometimes cited in discussions of ultra-low-power computing. We're not saying the Landauer limit is irrelevant to long-term research; we're saying it's irrelevant to engineering decisions in 2025. Current neuromorphic hardware operates 5–6 orders of magnitude above the Landauer limit. The practical constraints are entirely elsewhere.
The actual near-term physical constraints for neuromorphic inference are:
- SRAM retention current: Holding synapse weights in SRAM requires continuous refresh current proportional to array size. A 1 Mbit SRAM in 28nm process draws approximately 3–6 µW in retention mode. This is a floor that doesn't go away regardless of inference activity.
- Clock oscillator power: Any synchronous digital block needs a clock reference. A 32 kHz crystal oscillator draws 0.5–2 µW; a higher-frequency RC oscillator draws more. Fully asynchronous neuromorphic designs (event-driven without a system clock) avoid this, but most production chips still require a clock reference for I/O and management.
- Spike routing energy: Moving a spike from a source neuron to its post-synaptic targets consumes energy proportional to the Hamming distance in the routing network — the number of router hops traversed. On-chip routing consumes 0.1–0.5 pJ/hop; off-chip routing (multi-chip neuromorphic fabrics) consumes 5–20 pJ/hop.
A worked energy budget: acoustic anomaly detection
Consider a concrete deployment scenario: an acoustic anomaly detector for industrial machinery monitoring, installed on a motor housing in a manufacturing plant. The sensor must run for 36 months without battery replacement, sampling and classifying at 100 Hz (one 10 ms window per inference), reporting anomaly events over BLE to a nearby gateway (events expected at <1/hour under normal conditions).
# Energy budget allocation (µW, 36-month target)
# Total budget: 25 µW
# MEMS microphone (low-power mode, analog frontend)
mic_power = 3.5 # µW (typical MEMS in PDM mode at 16kHz, gated 10ms/window)
mic_avg = 3.5 * (10e-3 / (1/100)) # 10ms active per 10ms window = 100% duty = 3.5 µW
# SynSense Xylo inference core (64-neuron keyword/anomaly network)
xylo_inf = 18 # µW (inference active)
xylo_duty = 1.0 # continuous listening
xylo_avg = 18 # µW
# Supervisor MCU (32-bit, ultra-low-power, Stop2 mode with event wakeup)
mcu_sleep = 0.8 # µW (typical Stop2: ~0.3 µA at 3V ≈ 0.9 µW)
mcu_wake = 0.001 # avg µW (wakes ~1/hour for 5ms at 200 µA = negligible avg)
mcu_avg = 0.8 # µW
# BLE radio (CC2652R, burst TX at 5dBm, ~1 packet/hour)
ble_tx_e = 0.1 # µJ per packet
ble_freq = 1/3600 # 1 packet per hour = 2.8e-4 Hz
ble_avg = 0.1e-6 * (1/3600) * 1e6 # = ~0.028 µW ≈ negligible
# Total: 3.5 + 18 + 0.8 ≈ 22.3 µW
# Margin: 25 - 22.3 = 2.7 µWThis budget is tight but achievable. The Xylo core dominates at 18 µW because it's running continuously in listening mode. The 2.7 µW margin is thin — any design choices that increase Xylo's average current (larger network, higher sampling rate, increased inference temperature from self-heating) will blow the budget.
Where the budget breaks in practice
A team building an acoustic anomaly system for rotating equipment found that their initial prototype drew 38 µW average — 52% over budget — because their model had 256 neurons (too large for Xylo's lowest-power mode) and the MEMS microphone's PDM clock ran at 2.048 MHz rather than the 1.024 MHz that the NMC-compiled network actually required. Reducing the clock halved the microphone's dynamic power; pruning the network to 96 neurons (using dead-neuron elimination in the NMC compiler pass) brought Xylo average down to 21 µW. Final measured average: 24.8 µW — inside the 36-month budget with a 200 nW margin.
Energy-per-inference as the right metric
Average power is the right metric for battery life estimation, but energy-per-inference is the right metric for comparing inference implementations. At 18 µW continuous with 100 inferences/second, Xylo consumes 180 nJ per inference. An STM32L4 at 3.2 MHz (near minimum power for MEMS audio) running INT8 inference draws approximately 2 mW, for 20 µJ per inference at 100 Hz — a 110× difference in energy per inference.
The energy-per-inference metric reveals something important: the advantage is not purely from the neuromorphic architecture. A significant portion comes from the SNN's sparse activation — if the same model ran at 100% firing rate, energy-per-inference would approach 60–80 nJ at Xylo's reported SOP energy, and the advantage over INT8 would be only 25–40×. The compound of neuromorphic hardware + sparse spiking is what produces the full two-orders-of-magnitude gap.
Battery chemistry alternatives and their limits
CR2032 (lithium manganese dioxide) is not the only coin-cell chemistry. CR2016 stores ~75 mAh, CR2450 stores ~620 mAh but at 2.45 mm vs. 3.2 mm height, and ML2032 (rechargeable lithium manganese) stores ~65 mAh but can be trickle-charged from energy harvesting. For applications with any harvestable energy source (ambient light, vibration, thermal gradient), the effective capacity becomes unbounded — but harvest rates in indoor or deep-industrial environments are typically 1–10 µW, which only supplements a CR2032 rather than replacing it.
Supercapacitor-based storage is occasionally proposed for always-on sensor nodes, but the leakage current of commercially available supercapacitors (typically 1–10 µA self-discharge at 3V) exceeds the total inference budget. Supercapacitors work for burst-mode architectures that sleep deeply and wake to process events; they don't work as the primary long-term energy store for 36-month deployments.
The coin-cell budget is ultimately a design constraint that forces architectural clarity. The question "can this sensor node run for 3 years on a CR2032?" has a quantitative answer derivable from first principles, and that answer determines whether your inference architecture is viable before you've written a single line of model code.
