Research
Neuromorphic computing research
Our research team investigates spiking neural network theory, temporal encoding, online learning at the silicon edge, and hardware-software co-design for ultra-low-power inference. We publish in open venues and collaborate with academic partners.
Research focus
Four active research tracks
Spike encoding theory
How to represent continuous-valued sensor data as discrete spike trains without losing classification-relevant information. We study rate coding, temporal coding, and population coding strategies and their accuracy/efficiency tradeoffs across different workload types.
Online STDP learning
Spike-timing dependent plasticity (STDP) enables model weight updates directly on neuromorphic silicon without a training compute cluster. We're investigating online STDP for continual learning on non-stationary sensor distributions — a key requirement for deployed edge devices.
Multi-modal spike fusion
Industrial IoT sensors produce simultaneous vibration, thermal, acoustic, and IMU signals. Our work on multi-modal SNN fusion explores how spike timing relationships between asynchronous input streams can be exploited for higher accuracy without proportionally higher compute.
Hardware-software co-design
The NMC compiler's optimization passes were developed through tight feedback loops with silicon architects at partner fabs. This track studies how compiler-visible hardware annotations (spike bus width, timestep resolution, power mode transitions) should be exposed in the ISA and reflected in compiler IR.
Publications
Selected papers
Dead-Spike Elimination: Compiler-Side Pruning for Spiking Neural Networks Without Accuracy Regression
We introduce DSE, a compile-time pass that identifies and removes neurons whose spike rate falls below a calibration-derived floor. On 12 standard edge benchmarks, DSE achieves 31–47% binary size reduction with <0.3% top-1 accuracy delta.
Temporal Op Fusion for Spiking Workloads: Reducing Spike Bus Bandwidth by 2.4× on NT3000
Consecutive temporal convolutions sharing the same spike-time window are candidates for kernel fusion. We formalize the legality conditions, describe the fusion algorithm, and demonstrate 2.4× spike bus bandwidth reduction and 18% latency improvement on the NT3000 platform.
Population Coding vs. Rate Coding for IMU-Based Gesture Classification: An Empirical Study Across Five Neuromorphic Chips
We benchmark population and rate coding strategies across five neuromorphic chips on a 12-class IMU gesture dataset. Rate coding achieves higher accuracy with lower spike bandwidth on chips with large timestep windows; population coding favors chips with sub-10 µs timestep resolution.
A Compiler Intermediate Representation for Neuromorphic Silicon: Design Decisions and Lessons from NMC
We describe the design of the NMC compiler IR, including its spike-graph representation, hardware annotation system, and the tradeoffs considered during a 14-month co-design process with three silicon partners. Preprint; submitted for peer review.
Research collaboration
We collaborate with university neuromorphic computing groups and industrial partners. If you're working on SNN theory, edge hardware, or low-power inference systems, reach out.