Andrei Volkov, CEO. Santa Clara, February 2026.
Neurmorph was founded in 2021 with a specific thesis: that the right abstraction for ultra-low-power edge inference is the software stack, not the hardware. Neuromorphic silicon has been available in research form since the mid-2010s — Loihi, TrueNorth, SpiNNaker, and others — but deploying a model onto it required deep hardware expertise that most embedded engineering teams don't have and shouldn't need to acquire. If you had to write Lava compartment descriptors by hand to run a keyword spotter, neuromorphic hardware would remain a research curiosity regardless of how good its TOPS/W numbers were.
2025 was the year we found out whether that thesis produces something that engineers actually want to use. This is an honest accounting of what we shipped, where we fell short, and what changed our plans.
What we built
NMC Compiler v0.7 → v1.0
The NMC compiler went from a functional research prototype to a tool that an embedded systems engineer with no SNN background can use to get a compiled model onto neuromorphic hardware in an afternoon. The major milestones through the year:
- Q1: Stabilized the NMC-IR and the frontend
torch.fxingestion path. The compiler no longer required manual graph editing for batch-norm folding or activation replacement — both automated. - Q2: Added the HAL layer and the first production-ready Akida AKD1500 backend. Before this, Akida support existed but the backend was fragile — it failed on models with >4 layers. The HAL redesign fixed the root cause (synapse memory packing was using a single contiguous buffer that overflowed for larger models).
- Q3: Released the benchmark methodology v1 and ran the full benchmark suite on Loihi 2, Akida AKD1500, and Cortex-M7 baseline. This was the first time we had numbers we were confident publishing publicly. It also exposed calibration issues in our energy measurement setup that took 6 weeks to resolve — see the benchmark methodology post for details.
- Q4: Released the ANN-to-SNN conversion path with QAT fine-tuning, the
nrm.nnlayer library for native SNN training, and the Python-first API that is now the documented entry point. Compilation time dropped from 45–80 seconds to 3–6 seconds for typical-size models, primarily from eliminating redundant graph traversals in the optimization pass pipeline.
Hardware support expansion
We started 2025 with Loihi 2 as our only production-quality target. By end of year, Akida AKD1500 reached production quality and SynSense Xylo reached beta support (it compiles and runs; the energy measurement HAL integration for Xylo is still in progress). Innatera Spiketrum is in early investigation — we have the engineering interface documentation from their team, and the analog-target HAL design questions noted in our HAL post are the blocker.
Benchmark dataset VIB-1K
We collected and labeled 1,000 vibration recordings from industrial equipment for internal benchmark validation. This was more work than anticipated — coordinating recording sessions at facilities with operational equipment, calibrating sensor mounting procedures across different machine types, and doing the anomaly labeling required domain knowledge we sourced from mechanical engineers consulting with us. The dataset isn't released yet; we're cleaning the labeling inconsistencies in the Q3 batch before publication.
Three pilot programs
We ran three early-stage pilot programs with engineering teams during 2025. We're not identifying them — they're all at confidentiality, and we wouldn't want to imply endorsement. But their feedback shaped the product significantly.
The team building acoustic anomaly detection for rotating equipment taught us that the sensor integration layer is more important than the compiler API for practical users. They spent more time on microphone selection, preprocessing chain design, and field calibration procedures than on the SNN model itself. We built the sensor adaptation layer in the NMC SDK in Q4 directly in response to this feedback.
The team building DVS-based gesture recognition for a wearable taught us that latency matters more than we expected for interactive applications — and that our documentation on asynchronous vs synchronous inference modes was insufficient. Engineers defaulted to synchronous mode because it was more familiar, missed the latency advantage of event-driven execution, and then concluded SNNs were slower than their ANN baseline. This was entirely a documentation failure. We rewrote the quickstart guide to lead with the execution mode decision.
The team building autonomous inspection drones asked questions about multi-chip deployment, real-time DVS + IMU fusion, and thermal certification — none of which we had productized. We have roadmap items for all three, but the honest answer in 2025 was "not yet." Having specific engineering requirements from a real deployment helped us prioritize the roadmap substantially more rigorously than internal speculation.
Where we fell short
Multi-recurrent network support in the compiler was supposed to ship in Q3. It's in Q2 2026. The core issue (handling multi-hop recurrent connections in the scheduler without creating infinite dependency loops) turned out to have an edge case in the cycle-detection algorithm that we didn't find until we tried it on a real bidirectional LSTM-equivalent SNN. The fix is in the compiler but requires a regression test suite expansion before we're confident releasing it.
The Xylo backend took twice as long as estimated because SynSense's SDK had an undocumented memory alignment requirement for neuron state buffers that caused intermittent failures on inference runs over 1000 samples. Isolating this took longer than it should have. The lesson: undocumented hardware behavior consumes disproportionate debugging time, and the HAL shim needs better hardware validation tooling — specifically an automated compliance test that exercises edge cases in the memory layout.
Our training documentation assumed PyTorch familiarity but not SNN familiarity. The result was that engineers who were not computational neuroscientists struggled with surrogate gradient training concepts — specifically why training loss curves look different from standard classification training (the loss plateau at sub-threshold initialization, the spike-rate regularization term interacting with the accuracy loss). We're rewriting the training guide with more worked examples and diagnostic guidance.
The angel round
In February 2026 we closed a $100K angel investment. This is a small amount relative to the scope of the problem, and we're not treating it as a milestone in itself. It gives us runway to hire one additional engineer and to continue the pilot programs without disrupting core compiler development. The specific use: infrastructure work that doesn't generate IP but is essential — CI/CD for the benchmark suite, documentation tooling, and the Xylo backend stabilization.
What we're working on in 2026
Three technical priorities dominate our 2026 plan:
Multi-chip deployment support: The compiler's graph partitioner currently targets single-chip deployments. Extending it to reason about inter-chip routing energy and latency requires a significant refactor of the core allocation pass. This is the blocking dependency for models above ~100K neurons and for multi-modal fusion systems where the DVS, IMU, and audio streams require more compute than any single chip provides.
Temperature-characterized benchmarks: Publishing energy numbers at 25°C only is insufficient for industrial deployments. We're building a temperature-controlled test fixture for the benchmark suite that will produce measurements at 0°C, 25°C, 45°C, and 70°C. This data matters both for our customers' system designs and for validating our compiler's power model accuracy across temperature ranges.
On-device calibration tools: Field-deployed sensor nodes drift. Threshold calibration for DVS encoders and delta-threshold calibration for IMU encoders both need periodic adjustment in real deployments. The NMC runtime's current calibration tools require a laptop-connected calibration session. Moving this to an autonomous on-device calibration process — triggered by statistical anomaly detection in the input event stream — is the next runtime capability we're building.
The core bet remains the same as when we started: the bottleneck to neuromorphic inference adoption is the software stack, not the silicon. The silicon is getting better (Akida AKD1500 vs AKD1000, Loihi 2 vs Loihi 1), but the deployment tooling remains the barrier for embedded engineering teams. We intend to be the stack that removes that barrier.
