Supported Hardware
Three neuromorphic silicon targets are supported in NMC 0.9.x. Each requires a target-specific HAL shim implementation. The NT3000 eval kit is the recommended starting point for new integrations.
Chip specifications
| Specification | NT3000 | BrainPulse-2 | SynCore-V |
|---|---|---|---|
| Max neurons | 4,096 | 16,384 | 65,536 |
| Spike bus width | 64-bit | 128-bit | 256-bit |
| Timestep resolution | 20 µs | 10 µs | 5 µs |
| Internal SRAM | 512 KB | 2 MB | 8 MB |
| Active power | 38 mW | 95 mW | 280 mW |
| Idle power | 3.8 mW | 8 mW | 22 mW |
| HAL shim status | GA (v1.2) | GA (v1.0) | Beta (v0.7) |
| Eval kit available | Yes | On request | Q3 2026 |
NT3000 eval kit setup
The NT3000 eval kit ships as a USB-C connected board with 512 KB SRAM, 9-axis IMU sensor, and a USB-serial bridge for spike I/O. Firmware 1.2.0 is required for NMC 0.9.x compatibility.
Connect via USB-C, then run nmc doctor to confirm device detection. The green LED on the eval kit indicates power; the blue LED indicates USB enumeration.
If firmware is below 1.2.0, run nmc firmware update --device nt3000:usb0. The update takes approximately 30 seconds.
Run the quickstart compile + deploy flow to confirm a working end-to-end pipeline before integrating your own model.
HAL shim porting
To add support for a new neuromorphic chip, implement the 8-symbol HAL shim API. The stub template is included with NMC:
#include "nrm_runtime.h"
int hal_spike_read(spike_t *buf, size_t n) {
/* read from your chip's input bus */
return 0;
}
void hal_power_mode(nrm_power_t mode) {
/* set chip power state */
}
/* implement remaining 6 functions... */
After implementing all 8 symbols, compile with nmc build --hal hal_stub.c --target custom. Submit the HAL shim for review to request first-class target support in a future NMC release.
Hardware roadmap
- SynCore-V GA — Q3 2026. 65K neuron target with 5 µs timestep resolution and eval kit shipping.
- Multi-chip spike routing — Q4 2026. Runtime support for spike bus bridging across multiple chips in a single device.
- Cortex-M55 simulation target — NMC 0.10. Allows testing .snn binaries on standard ARM hardware before neuromorphic silicon is available.